AN ENTRY FOR THE 9th ANNUAL (2012) "HUMIES" AWARDS FOR HUMAN-COMPETITIVE RESULTS PRODUCED BY GENETIC AND EVOLUTIONARY COMPUTATION HELD AT THE GENETIC AND EVOLUTIONARY COMPUTATION CONFERENCE (GECCO) ON JULY 7-11, 2012 IN PHILADELPHIA (1) TITLES: (I) LAYGEN II – Automatic Analog ICs Layout Generator based on a Template Approach (II) LAYGEN II – Automatic Layout Generation of Analog ICs based on Template Descriptions and Evolutionary Computation (2) AUTHORS: For (I) and (II): Ricardo Martins, ricmartins@lx.it.pt For (I): Nuno Lourenço, nlourenco@lx.it.pt Nuno Horta, nuno.horta@lx.it.pt Physical address for all the authors: Instituto de Telecomunicações/Instituto Superior Técnico, Av. Rovisco Pais 1, 1049-001 Lisboa, Portugal (3) CORRESPONDING AUTHOR: Ricardo Martins (4) ABSTRACT: (I) This paper describes an innovative analog integrated circuit layout generation tool, LAYGEN II, based on evolutionary computation techniques. The designer provides the high level layout guidelines through an abstract layout template. The template contains placement and routing constrains independently from technology, and can be used hierarchically in the definition of templates for complex circuits. LAYGEN II uses this expert knowledge to guide the evolutionary optimization kernels during the automatic layout generation in the target technology. The routing task of the proceeding can range from a template-based approach to a full automatic generation, if only connectivity is provided. The LAYGEN II tool is demonstrated for the layout generation of two typical analog circuit structures and the results validated by Calibre® design rule check tool. (II) The work presented in this report belongs to the scientific area of electronic design automation and addresses the automatic generation of analog integrated circuit (IC) layout. An innovative design automation tool based on template descriptions and on evolutionary computation techniques, LAYGEN II, which stems from LAYGEN, was developed to validate the proposed approach giving special emphasis to the reusability of expert design knowledge and to the efficiency on retargeting operations. LAYGEN II intends to be integrated in the bottom- up physical synthesis path of an analog design automation process, along with an in-house tool, GENOM-POF, which performs automatic IC sizing in the top-down electrical synthesis path of the flow. The designer specifies the sized circuit-level structure, the required technology and, also, provides the technology independent high-level layout guidelines through an abstract layout description, henceforward called template. The generation proceeds in the traditional way, first placement and then routing. For placement, the topological relations present in the template are mapped to a non-slicing B*-tree layout representation, and the tool automatically merge devices and ensures that the design rules are fulfilled. The router optimization kernel consists of a modified version of the multi-objective evolutionary algorithm, NSGA-II, and uses a built-in design rule check (DRC) as evaluation engine. The automatic layout generation is here demonstrated using the LAYGEN II tool for two selected typical analog circuit structures, namely, a fully-dynamic comparator and a single- ended folded cascode amplifier. The layouts were generated for two design processes, UMC 130 nm and AMS 350 nm, and the output provided is a GDSII stream format, a file standard for data exchange of IC layout. Automatic generation processes were performed in less than 5 minutes, which allow for the designer to quickly obtain a first cut solution. The results were validated using the industrial grade verification tool Calibre® to run DRC, layout versus schematic, and also extraction, in addition post-layout simulations were successfully performed. (5) CRITERIA: (D) The result is publishable in its own right as a new scientific result — independent of the fact that the result was mechanically created. (E) The result is equal to or better than the most recent human-created solution to a long-standing problem for which there has been a succession of increasingly better human- created solutions. (G) The result solves a problem of indisputable difficulty in its field. (6) WHY THE RESULT SATISFIES THE CRITERIA: “In digital integrated circuit (IC) design several electronic design automation tools and design methodologies are available to help the designers keeping up with the new capabilities offered by the integration technologies, while analog design automation tools are not keeping up with the new challenges created by technological evolution. This is one of the reasons why analog design is many technology nodes behind leading-edge digital. Due to the lack of automation, analog designers keep exploring manually the solution space, this method causes longer design times than digital and allied to the non-reusable nature of analog IC design, make it a cumbersome task.” – Quoting (II) (D) The achieved results are publishable in their own right as new scientific results once the presented approach, new in literature, implements a general, robust and automated analog integrated circuits layout generation. The generated layouts compete with the best published solutions in terms of: (1) solution robustness, once the strict technological rules are fully verified during the automatic generation; (2) solution quality, once that automatically implements specific layout operations used by expert analog designers, e.g., abutment, in order to improve the solution; and (3) solution flexibility, by decreasing production cost due to the design time reduction, given the fast generation and the efficiency on redesign operations the productivity is highly increased. (E) The results of the presented approach are equal or better than the state-of-the-art academia and commercial solutions for the automatic generation of analog integrated circuit layouts, once, it implements an evolutionary optimization kernel to attain optimal layout solutions enhancing the performance and quality of the generated layouts. Moreover, the approach is general, applied to any class of circuits, and technology independent allowing retargeting operations for either different specifications in the same technology or moving to different technologies. (G) The approach solves a problem of indisputable difficulty in the field of analog integrated circuit design, since from an industrial point of view the application of electronic design automation tools in analog layout synthesis is still far away from being a reality. The analog layout problem includes both placement and routing tasks, which means generating the representations for each circuit structure in a technological process with several layers. Moreover, the solutions must comply with the strict technological design rules, which all together lead to huge decision and solution space. The presented approach produces layout solutions and performs redesign operations in few minutes, for cases where a designer can easily take hours using the traditional layout editors, since in the handmade design the solution is iteratively changed until no design rule is violated. (7) CITATION: (I) R. Martins, N. Lourenço, N. Horta, “LAYGEN II – Automatic Analog ICs Layout Generator based on a Template Approach”, Genetic and Evolutionary Computation Conference (GECCO 2012), July 2012, Philadelphia, USA. (II) R. Martins, "LAYGEN II – Automatic Layout Generation of Analog ICs based on Template Descriptions and Evolutionary Computation", Master thesis in Electrical Engineering, May 2012, Instituto Superior Técnico 2012, Lisboa, Portugal. http://cascais.lx.it.pt/~icsg/Thesis2012/ThesisRMartins2012.pdf (8) STATEMENT OF PRIZE DISTRIBUTION: Any prize money is to be divided equally among the co-authors. (9) COMPARISON TO OTHER HUMAN-COMPETITIVE ENTRIES: (1) The approach solves a problem of indisputable difficulty for the ever-increasing integrated circuits industry and considering challenging technologies. (2) The approach beats state-of-the-art analog IC design automation solutions from both academia and industry, once, from the best of our knowledge, no other design automation tool is implementing a automatic layout generation in such a general, flexible and robust approach. All the results are validated in Mentor Graphics’ Calibre® DRC tool, a main reference in the ICs design when the development is intended for fabrication. (3) Post-layout simulations proved that the achieved solutions present equal or better performance than handmade layouts. But the huge improvments are in terms of design time since the presented approach avoids the traditional layout editors, the problem can be described and the solution obtained in about 3 to 5 times faster than the manual design. For the redesign operations, the proposed methodology is used to obtain retargeted solutions within minutes, more than 10 times faster than the typical handmade design. This fast generation leads to a reduction in terms of time-to-market and, therefore, design costs.