AN ENTRY FOR THE 9th ANNUAL (2012) "HUMIES" AWARDS FOR HUMAN-COMPETITIVE RESULTS PRODUCED BY GENETIC AND EVOLUTIONARY COMPUTATION HELD AT THE GENETIC AND EVOLUTIONARY COMPUTATION CONFERENCE (GECCO) ON JULY 7-11, 2012 IN PHILADELPHIA 1) PAPER TITLE GENOM-POF: Multi-Objective Evolutionary Synthesis of Analog ICs with Corners Validation 2) AUTHOR Nuno Lourenço, nlourenco@lx.it.pt Nuno Horta, nuno.horta@lx.it.pt Physical address for all: Instituto de Telecomunicações/Instituto Superior Técnico, Av. Rovisco Pais 1, 1049-001 Lisboa, Portugal 3) CORRESPONDING AUTHOR Nuno Lourenço 4) ABSTRACT In this paper, a multi-objective design methodology and tool for automatic analog IC synthesis, which takes into account the effects of process variations, is presented. By varying the technological and environmental parameters, the robustness of the solutions is enhanced. The automatic analog IC sizing tool, GENOM-POF, was implemented to demonstrate the methodology and to verify the effects of corner cases on the Pareto optimal front (POF). The impacts of NSGA-II parameters when applied to analog circuit sizing were investigated, and three different design strategies were tested in a benchmark circuit, showing the effectiveness of multi-objective design of analog cells. 5) CRITERIA (D) The result is publishable in its own right as a new scientific result — independent of the fact that the result was mechanically created. (E) The result is equal to or better than the most recent human-created solution to a long-standing problem for which there has been a succession of increasingly better human-created solutions. (G) The result solves a problem of indisputable difficulty in its field. 6) WHY THE RESULT SATISFIES THE CRITERIA (D) The achieved results are publishable in their own right as new scientific results once the presented approach, new in literature, implements a robust multi-objective optimization approach including extreme technological and environmental variations, i.e., achieved performance (e.g. less power and/or less area) is robust and optimal and, therefore, competes with the best published solutions in terms of sizing of analog integrated circuits. (E) The results of the presented approach are equal or better than the state-of-the-art academia and commercial solutions for automatic analog integrated circuit sizing, once, it not only implements an optimization-based approach, based on modified NSGA-II implementation, using an electrical simulator as evaluation engine, which guarantees high accuracy for the solutions, but also embeds extreme parameter validations in a fully automatic and robust approach. The search quality surpasses the state-of-the-art solutions by combining a coarse grain optimization, first, and then a fine grain optimization where the behavior with all specified extreme variations are validated. Moreover, the approach is general in the sense it applies to a broad range of analog integrated circuits topologies. Finally, the results are not oversized by considering extreme variations once this are requirements for robustness imposed by industry when dealing with high performance circuits. (G) The approach solves a problem of indisputable difficulty in the field of analog integrated circuit design. The problem of sizing analog integrated circuits with multiple performance measures and several design variables is extremely complex, specially, when trying to optimize performance and minimize costs. The complexity of the problems can be measured in terms of the number of objectives (usually large or equal to 2), the number of constraints (usually dozens, e.g., gain > C1, unity gain bandwidth > C2, phase margin > C3, overdrive voltages applied to each transistor being sized, etc.), the number of optimization variables (usually dozens, e.g., widths and length of each transistor being sized), which all together lead to huge non-linear decision and objective spaces. The presented approach produces, fully automatically, comprehensive optimal and robust solutions in few minutes for cases, where a designer can easily take hours with an iterative process controlled manually. 7) CITATION N. Lourenço, N. Horta, “GENOM-POF: Multi-Objective Evolutionary Synthesis of Analog ICs with Corners Validation”, Genetic and Evolutionary Computation Conference (GECCO 2012), July 2012, Philadelphia, USA. 8) STATEMENT OF PRIZE DISTRIBUTION Any prize money is to be divided equally among the co-authors 9) COMPARISON TO OTHER HUMAN-COMPETITIVE ENTRIES (1) The approach solves a problem of indisputable difficulty for the integrated circuits industry and considering the most challenging technologies. (2) The approach beats state-of-the-art analog IC design automation solutions from both academia and industry (commercial tools), once, from the best of our knowledge, no other design automation tool are implementing such a restrictive and realistic design approach – multi-objective with extreme technological and environmental variations together with a high accuracy evaluation engine. (3) The achieved optimally sized solutions beat humans in terms of performance and design time. Solving this no trivial industry problem automatically using multi- objective evolutionary strategy leads to a 5-10X reduction in terms of design time (even if the setup time is included).